Intel to release Eight-Core Xeon Next Month
written by Madhukar
at January 31, 2009
Macworld is reporting that Intel plans to detail an eight-core Xeon processor at the International Solid-State Circuits Conference in San Francisco next month.
Macworld speculates that the impending eight-core Xeon will probably be Intel's Nehalem EP processor, an upcoming chip designed for dual-socket workstations and servers. Scheduled for a release during early 2009, the Nehalem EP processor will use Intel's Quick Path Interconnect, eliminating the front-side bus and allow more data to flow between the processor and the other components installed in the system. The Nehalem EP processor will also include an integrated memory controller as well.
Last week, Intel reported that restructuring plans included the termination of five older factories, affecting between 5,000 and 6,000 workers worldwide, although some would stay on board and shift to other facilities. The company said restructuring would begin immediately and continue until the end of 2009. The affected facilities include two assembly test facilities in Penang, Malaysia and one in Cavite, Philippines. Production will halt at Fab 20 located in Hillsboro, Oregon; wafer production operations will cease at the D2 facility in Santa Clara, California.
Wednesday the company said it planned to cut 100 to 200 additional jobs at its Rio Rancho plant in New Mexico within the next few months. However, Intel reassured that although it will consolidate and streamline older operations, the restructuring would no impact the deployment of 45-nm and 32-nm manufacturing capacity.
The International Solid-State Circuits Conference will take place on February 8-12 in San Francisco. Intel will make its presentation during Session 3 at 1:30 PM PST, Monday, February 9th, entitled "A 45nm 8-Core enterprise Xeon Processor."
"An 8-core 16-thread enterprise Xeon processor has 2.3B transistors in 9M 45nm CMOS," reads the Conference program (PDF). "The I/O links the use per-lane TX and RX compensation to enable operation up to 6.4GT/s. Vertical and horizontal splines keep the undercore clock skew under 19p before engaging the compensation. Core and cache shut-off techniques are used to minimize leakage."
Intel will also make other presentations at 2 pm (A Family of 45nm IA Processors) and 3:15pm (Dynamic Frequency-Switching Clock System on a Quad-Core Itanium Processor."
Source: Toms Hardware